New generation of Insulated Gate Bipolar Transistors (IGBTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) power switches (both Superjunction and wide band gap ones) are characterized by a gate-drain capacitance (CGD) which is extremely non-linear along the drain-source voltage VDS range. Especially in superjunction technology, the gate-drain capacitance CGD has a large variation due to voltage. This capacitance is fundamental for the switching speed transients.
In a hard switching application, the power switch is turned on when VDS is high, or in other words hard switching occurs when there is an overlap between high voltage VDS and high current IDS during a switching event (e.g., during a turn on switching event) of the power transistor. This overlap causes energy losses which can be minimized by increasing di/dt and dV/dt (i.e., the slope of current IDS and the slope of voltage VDS. Thus, a very steep VDS voltage transient, called dV/dt, may be present.
In standard planar technology, the fast dV/dt transient is present but is mitigated by the miller multiplication effect on CGD. In fact, a gate diver output current Io+, used to raise (i.e., charge) the gate voltage of the power transistor during the turn on transient, fully flows into CGD during the dV/dt and the gate voltage appears flat forming the “miller plateau.” If the speed of dV/dt doubles, the capacitance CGD doubles its apparent value and the system self-regulates.
For this reason, when using power switching devices, the output switching starts with a very high dV/dt (when VDS voltage is high) and it finishes with a long slow tail in the last few volts (when CGD becomes large). FIG. 1 illustrates, on the left, a dV/dt behavior in power switches, and, on the right, a schematic representation of an IGBT 1. In particular, FIG. 1 shows, on the left, a transient diagram of VDS (i.e., dV/dt) and IDS (i.e, di/dt) during a turn on switching event. During the turn on switching event, VGS increases as CGD is charged. Once VGS is equal to the threshold voltage Vth, current IDS begins to flow. FIG. 1 further illustrates, on the right, a schematic diagram of a power transistor 1 showing the parasitic capacitance CGD, the drain-source voltage VDS, the drain-source current IDS, and the gate-source voltage VGS.
As can be seen in the diagram on the left, the VDS voltage transient, called dV/dt, is initially very steep and fast and then changes to finish with a long slow tail for the last few volts. This dynamic behavior is typical of transistor devices, especially in superjunction devices, and both fast and slow dV/dt transients are not wanted for a few of reasons.
First, the transistor switching characteristic is reflected on the motor phase making these power devices not properly acceptable for motor manufacturers because of the hard stress reflected on the motor phase. In particular, the fast dV/dt stresses the motor and in particular the insulator material between the motor windings. Thus, the fast dV/dt transient, can compromise or even damage the insulator material between the motor windings.
Second, steep dV/dt values can generate problems in qualifying the final system from an electromagnetic interference (EMI) and an electromagnetic compatibility (EMC) point of view.
Third, low or slight dV/dt values worsen the switching losses since losses continue as long as the dV/dt tail is above zero.
In summary, when using transistor switches, it becomes difficult to find the correct single value Io+ current to turn on the power transistor since the switching speed appears to be too fast (i.e., fast dV/dt) or too slow (i.e., dV/dt slow tail) in different moments of the same switching event. Furthermore, being a parasitic capacitor, CGD is not controlled in production. This, causes wide lot-to-lot variations on the limit values.
In view of the above, a detection and driving strategy may be desirable in order to reduce this transient in a dV/dt value suitable for motor drive while at the same time limiting the switching losses in the power inverter.